The present invention relates to Integrated Circuit (IC) semiconductor devices and structures and methods for the manufacture thereof. More particularly it relates to a process of forming structural features on semiconductor wafers resistant to cracking within the interconnect stacks. The structural features are adapted to prevent damage to semiconductor devices caused by subdivision of semiconductor wafers into individual chips by a process known as dicing. In addition, this invention relates to prevention of chip packaging interaction fails in interconnect structures formed during Back End Of Line (BEOL), interconnect, processing of semiconductor devices, late in the manufacturing process.
Microelectronic semiconductor IC devices such as Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS FET) devices and the like are manufactured in a complex process in which numerous separate electronic devices are formed. Such processes of manufacture, which produce large numbers of such electronic devices, are referred to as Very Large Scale Integration (VLSI) processes. After many processing steps, the monolithic, semiconductor wafers must be subdivided by dicing to form the numerous, individual semiconductor chips.
Referring to FIG. 1A a schematic, sectional, fragmentary, elevation is shown of a prior art type of CMOS FET, monolithic, semiconductor device 10 in an advanced stage of manufacture of the type which includes numerous VLSI electronic IC devices. However, for convenience of illustration and explanation, the only portion of the semiconductor device 10 that is shown in FIG. 1A includes a first chip 10A which is juxtaposed with a second chip 10B. Those two chips represent a large number of such chips included elsewhere in the semiconductor device 10. Semiconductor devices including the first chip 10A and the second chip 10B are formed in the active device Front End Of Line (FEOL) region within a semiconductor substrate 12 and upon the top surface 16 thereof. The substrate 12 usually comprises a single silicon (Si) semiconductor wafer. FIG. 1B shows the first chip 10A separated from the second chip 10B, after performing a dicing step, as described below.
Initially, an active device FEOL region 14 (shown in an abstract form as a layer with features obscured) is formed on the top surface 16 of the substrate 12 during FEOL processing, prior to BEOL processing. The active device FEOL region 14 contains structures, e.g. CMOS FET devices (not shown for convenience of illustration) some of which are formed in the substrate 12 and some of which are formed upon the top surface 16 thereof. As will be well understood by those skilled in the art, it is conventional for a CMOS FET device to reach above the top surface 16 of the substrate 12. Subsequently, during Back End Of Line (BEOL) processing steps, an interconnect layer 15 (also shown in an abstract form as a layer for convenience of illustration) is formed over the top surface 17 of the active device layer 14. The interconnect layer 15 contains metallic structures, typically composed of copper, that provide external interconnections (interconnects) which are formed in many levels of Intra-Level Dielectric (ILD) layers (i.e. an ILD stack) for electrically connecting the numerous FET devices, e.g. the first semiconductor chip 10A (on the left) and the second semiconductor chip 10B (on the right) to external devices, as will be illustrated in FIGS. 5A/5B, etc. and described below with reference thereto. The interconnect layer 15 includes a left side portion 15A and a right hand portion 15B which are to be separated by dicing. The result of such dicing is shown in FIG. 1B.
At the base of the first chip 10A (on the left of FIGS. 1A/1B) is a first substrate portion 12A supporting a first active device layer 14A on surface 16 thereabove. Similarly, the left side portion 15A of the interconnect layer 15 is formed above the first active device layer 14A. At the base of the second chip 10B, on the right, is a second substrate portion 12B supporting a second active device layer 14B on surface 16 thereabove. Similarly, the right side portion 15B of the interconnect layer 15 is formed above the second active device layer 14B. A dicing channel 130 shown in phantom in FIG. 1A prior to dicing is located in the space between the first and second chips 10A/10B. FIG. 1B shows the dicing channel 130 after the step of dicing has been performed separating the chip 10A from the chip 10B. Although it is not shown, for convenience of illustration, the dicing channel 130 surrounds each of the chips as is well known to those skilled in the art.
In addition, separate first and second crackstops 50A/50B are formed in the interconnect layers 15A/15B surrounding the perimeter of each interconnect layer 15A/15B. Each of the first and second crackstops 50A/50B is located between the dicing channel 130 and the active area (AA) of each of the chips 10A/10B, respectively. The crackstops 50A/50B are provided along the perimeters of the chip 10A and chip 10B to protect each interconnect layer 15A/15B from damage that would otherwise be likely to be caused by cracking. Each of the crackstops 50A/50B extends entirely through the interconnect layer 15 to the top surface 17 of the active device layer 14.
As is conventional in BEOL processing, at least one layer of dielectric material is formed in the interconnect layer 15 over the active device FEOL region 14 of the semiconductor device 10. Generally, such a dielectric layer(s) is fabricated so that metal interconnect lines (described below) may be formed thereon to provide external electrical connections to the FET devices. Copper, tungsten, and aluminum, or alloys thereof, and other like metals are commonly used to form the interconnect lines. IC chips having multiple bonded dielectric layers as well as multiple layers of interconnect lines disposed thereon are well known in the art.
Often the density of the material of the dielectric layers is not uniform throughout. Film stresses and interfaces in the material allow microcracks to propagate within the dielectric layers until the microcracks encounter metal structures, e.g. vertically extending vias and horizontally extending interconnect lines. Because such metal structure are very thin, such cracks usually severely affect interconnect lines and vias causing fracture thereof resulting in chip failure since the external connections to chip elements have been broken. The dicing process often causes cracks that damage active areas of chips such as chips 10A/10B. Thus to prevent such catastrophic damage, as is conventional, crackstops 50A/50B are provided along the perimeter of the BEOL structures 15A/15B of each of the chips 10A/10B to protect them from potential damage caused by cracking.
The manufacture of devices such as the semiconductor device 10 requires the performance of many preliminary steps, such as FEOL steps that form the active device FEOL region 14 in the substrate 12 and thereabove followed by BEOL step during which the interconnect layer 15 is formed over the active device layer 14.
Eventually after performance of many FEOL and BEOL processing steps the monolithic, semiconductor device 10 containing the numerous, VLSI semiconductor chips is subdivided by a dicing process to form individual, separate chips. During the dicing process the chips which have been formed on the substrate 12 are separated from each other. For example the first chip 10A is separated from the second chip 10B. The dicing process is confined to making cuts in intermediate spaces such as the dicing channels 130, which are located between the first chip 10A and the second chip 10B.
In FIG. 1B, as stated above, the first chip 10A is shown separated from the second chip 10B, after performing a conventional dicing step performed by cutting down through the semiconductor device 10 from the top surface 18 of the BEOL structure 15 to the bottom surface 19 of the substrate 12 within the dicing channel 130 between the chips 10A/10B with the cut at the location of the dicing channel extending all the way down through the bottom surface of the substrate 12. During dicing, a set of peripheral diced chip edge surfaces 110 are formed on the vertical edges of each of the chips 10A/10B approximately along the edge of the chip-to-chip dicing channel 130 on the sidewalls of the diced chips 10A/10B where material has been removed.
Manifestly, the dicing process is destructive because it generates stresses and strains which often induce microcracks in the semiconductor substrate 12, the active device layer 14, and/or the dielectric layers in the interconnect layer 15. As microcracks occur in a silicon substrate 12 they usually propagate very rapidly thereby causing failures that show up in the initial testing. Microcracks in layers of dielectric material such as those found in the interconnect layers 15 propagate more slowly and tend to lead to delayed failures including chip packaging interaction fails, i.e. failures which occur after devices are in the field. Chip packaging interaction failures, as well as failures in the field, are very expensive and disruptive. Thus there is a very significant need to provide a process that reduces propagation of microcracks in dielectric layers.
A high priority goal of VLSI manufacturing is production of a high yield of chips from each wafer, thereby assuring commercial profitability. As the number and complexity of chips per wafer increases, the yield often decreases proportionally. Accordingly, it is highly desirable to minimize the number of defective chips.
In the FEOL steps, electronic devices such as CMOS FET devices are formed by a series of steps including creation of photolithographic masks which used to form patterns on the semiconductor substrate 12. Etching and deposition is performed with materials being introduced in blanket form onto exposed surfaces in, on, and/or above the substrate 12 by deposition or growth of materials in blanket form or in specific regions by introduction of material onto surfaces through open mask windows. In other steps, material is removed from surfaces and structures subtractively, e.g. by etching with or without etching through open mask windows.
In the BEOL processing steps, the IC fabrication process continues by building interconnects containing multiple layers of wiring and dielectric passivation layers on the top surface 17 of the active device FEOL region 14 that contains the semiconductor devices. As stated above, the metallic structures for providing external interconnections (interconnects) are formed in many levels of ILD layers for electrically connecting the numerous devices on the semiconductor chips 10A/10B to external devices using similar processing techniques. The conventional barrier structures 50A/50B in FIGS. 1A/1B, known as crackstop/MOB (Moisture Oxidation Barrier) structures, are formed on the periphery of the interconnect layers 15A/15B of each chip 10A/10B adjacent to the dicing channel 130 where the dicing is to occur. In fact a conventional barrier structure 50A/50B may comprise a crackstop or MOB structure. Then upon completion of substrate-level FEOL and BEOL processing, the semiconductor devices 10A/10B are ready to be divided into individual semiconductor chips by dicing through the dicing channel 130 to provide separation into individual chips including the first chip 10A and the second chip 10B.
As stated above, FIG. 1B depicts the prior art semiconductor device 10 of FIG. 1A after dicing thereof, during which the semiconductor device 10 has been split into the first chip 10A and the second chip 10B by cutting through the layers of the device in dicing channel 130 between the first and second chips 10A/10B. The result of the dicing process is that the active device FEOL region 14 and the interconnect stack 15 of FIG. 1A are split in two. On the left the first chip 10A includes a first active device 14A and a first chip interconnect 15A. On the right the second chip 10B includes a second active device 14B and a second chip interconnect 15B. However, as stated above, the problem with dicing of semiconductor devices is that the dicing process generates stresses and strains which can lead to cracking. The dicing process often causes cracks that damage Active Areas (AA) of the chips. Such cracking can damage the devices and metallization on the semiconductor chips. To prevent such damage, the crackstops 50A/50B have been provided along the perimeter of the chips 10A/10B to interrupt propagation of cracks beyond them.
As stated above, dicing damage causes cracking within the interconnect stacks 15A/15B of ILD and metallization layers. Such dicing-initiated cracking can affect one or more of the many ILD layers in a BEOL structure 15, resulting in a loss of structural integrity. The cracking problem is exacerbated upon a subsequent step of joining semiconductor chips 12A/12B, etc. to packaging substrates. Moreover, the problem is at its worst when the packaging substrate comprises an organic material as compared with a ceramic packaging substrate. The delta value of the Coefficient of Thermal Expansion (CTE) mismatch between different assembled materials in the device being manufactured causes greater strains and stresses on the semiconductor chips, which, in turn, generate the growth of cracks within layers in a BEOL structure.
An object of this invention is to provide a structure that inhibits cracks from damaging the BEOL structure of a chip or even inhibits cracks from damaging the Active Area below the BEOL structure in the chip.
The active areas AA of the chips 10A/10B are located in each of the two substrate regions 12A/12B, including both the interconnect stack 15A/15B and the active device layer 14A/14B and inside the crackstops 50A/50B. A typical crackstop 50A/50B is a solid metal structure formed in a trench spanning all interconnect levels or a plurality of solid metal structures spanning all interconnect levels around the periphery of each chip on a semiconductor wafer.
New Failure Mechanisms
In the past, the weakest material in an IC structure has been the material of the substrate 12, which is typically composed of a semiconductor material such as monocrystalline silicon. However, the increased demand for improvement in the performance of ICs has led to the introduction of low dielectric constant (low-k) ILD layers in the interconnect stack 15. The low-k materials have less mechanical (cohesive) strength than traditional dielectrics such as silicon dioxide (SiO2).
In particular, FIG. 2A is a chart which shows that the cohesive strength value of an ILD layer of a semiconductor chip decreases as a function of decreasing of the dielectric constant value. There is a problem, that the contemporary strategy of lowering of the cohesive strength of the ILD layer has resulted in the shifting of the location of the weakest material in an integrated structure from the substrate (which is typically monocrystalline silicon) to the ILD layers. Thus, the result of the strategy of use of low-k materials in the ILD layer has introduced new failure mechanisms during the steps of dicing of wafers into chips and subsequent packaging and reliability testing.
A key requirement for stopping these new failure mechanisms is to limit the propagation distance, i.e. the Delamination Length (DL), to which a flaw generated during the dicing process can propagate before it encounters the crackstop/MOB structure. While there are a number of potential solutions to this problem, in the past solutions which have been employed have required either a loss in productivity (reduction in number of chips per wafer) or a loss in I/O density due to a redesign of a Controlled Collapse Chip Connection (C4) layouts.
FIG. 2B is a chart which shows the energy imparted to dielectric layers due to the packaging material as a function of the defect size, i.e. length, of a flaw which is created during dicing and which propagates during reliability stressing. As the flaw extends to greater lengths, there is a monotonic increase in the energy release rate tending to drive the flaw towards failure. If a flaw is allowed to grow large enough, sufficient energy will build up to (first) either break through the crackstop/MOB structure or (second) dive down into the silicon (Si) substrate and into the Active Area (AA) of the chip. Therefore the most robust path to ensuring reliability is to limit the flaw size.
Commonly assigned U.S. Pat. Nos. 5,530,280 and 5,665,655 of White, both entitled “Process for Producing Crackstops on Semiconductor Devices and Devices Containing the Crackstops” describe a process for making semiconductor device with a crackstop formed by a groove filled with metal surrounding the active region on a chip at the same time as other functional metallization is occurring. Then after final passivation selective etching removes the metal in the groove. The groove passes through the surface dielectric or the semiconductor substrate, or is replaced by hollow metal rings stacked through multiple dielectric layers.
Underfill layers have been employed in IC packaging to protect the Surface Mount Devices (SMDs), i.e. IC chips bonded to a Printed Circuit (PC) board with solder ball joints. During the mounting process, the solder balls on SMD IC chips are aligned with electrical contact pads on the PC board. Subsequently the PC board is heated causing the metal of the solder ball joints to flow, joining the chips with contact pads on the PC board. Next an underfill epoxy material is introduced between the chip and the board. Then the PC board is reheated to cure the epoxy, forming a seal around the chip to protect it from moisture and to help to preserve the integrity of the solder balls joints.
U.S. Pat. No. 6,822,315 of Kelkar et al. entitled “Apparatus and Method for Scribing Semiconductor Wafers Using Vision Recognition” refers to U.S. Pat. No. 6,245,595 entitled “Techniques for Wafer Level Molding of Underfill Encapsulant,” as describing use of a cured or a partially cured epoxy underfill type of layer on the top surface of a wafer before it is diced rather than after dicing and before mounting on a PC board. The epoxy layer, that protects the chips during handling, is formed on the top surface of the wafer and includes an epoxy resin, a hardener, a catalyst, a filler material (e.g. silicon particles) and a dye. The filler material reduces the CTE of the epoxy to match that of the PC board upon which the micro SMDs will be mounted. As temperature variations occur, the PC board and epoxy expand and contract at similar rates. Without the filler material, the rates of expansion and contraction would be different, resulting in potential joint failures, over time.
Commonly assigned U.S. Pat. No. 6,566,612 B2 of Brouillette et al entitled “Method for Direct Chip Attach by Solder Bumps and an Underfill Layer” states that in a conventional flip chip process, an underfill material with thermal expansion characteristics which are CTE matched to solder by using fillers in the underfill composition is frequently dispensed after chip-substrate attach by a capillary action through the gap between the chip and the substrate.
U.S. Patent Application 20060125119 of Xiao et al. entitled “B-Stageable Underfill Encapsulant and Method for its Application” describes several compositions of underfill materials applied directly onto semiconductor wafers before dicing the wafers into individual chips.
U.S. Pat. No. 6,492,247 B1 of Guthrie et al. (commonly assigned) entitled “Method for Eliminating Crack Damage Induced By Delaminating Gate Conductor Interfaces In Integrated Circuits” describes managing crack damage in the ICs to reduce or eliminate crack propagation into the IC active array by providing a defined divide or separation of the IC gate conductor from the IC crackstop or edge. The method is employed to manage crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process.
Commonly assigned U.S. Patent Application No. 2004/0129938 A1 of Landers et al. entitled “Multi-Functional Structure for Enhanced Chip Manufacturibility & Reliability for Low K Dielectrics Semiconductors and a Crackstop Integrity Screen and Monitor” describes an on-chip redundant crackstop providing a barrier to prevent defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure permit wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip to monitor barrier integrity.
U.S. Patent Application No. 2005/0208781 A1 of Fitzsimmons et al. (commonly assigned) entitled “Crackstop With Release Layer For Crack Control In Semi-conductors” describes forming an IC device with vertical interfaces (adjacent to a crackstop on the perimeter of a chip) which controls cracks generated during steps such as side processing of the device, e.g. dicing, and controls cracks when the chips are in service by preventing a crack from penetrating the crackstop. The vertical interface is comprised of a material that prevents cracks from damaging the crackstop by deflecting cracks away from penetration of the crackstop, or by absorbing the generated crack energies. The vertical interface may be a material that allows advancing cracks to lose enough energy so they cannot penetrate the crackstop. The vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material. There can be voids in the material such as an ultra low-k dielectric layer formed in a vertical trench juxtaposed with the crackstop.
The Abstract of Japanese Patent Publication 2004-111946 of Kubo et al entitled “Laser Dicing Equipment and Dicing Method” describes use of laser heads to perform dicing. For example, the laser heads are indexed from both ends to the center of a wafer, or from the center of the wafer to both ends. Alternatively, the laser heads are arranged separated from each other by a prescribed number of lines and indexed in the same direction, and two lines are carved into the wafer throughout its surface.
US2006/0057822A1 (commonly assigned) of Daubenspeck et al. entitled “Chip Dicing” describes a semiconductor structure and method for chip dicing, wherein first and second device regions of first and second chips are formed in and at the top of the semiconductor substrate. The chips are separated by a semiconductor border region of the semiconductor substrate. N interconnect layers are formed directly over the semiconductor border region and first and second device regions, where N is a positive integer, with each of N interconnect layers comprising an etchable portion directly above the border region. Etchable portions of the N interconnect layers form a continuous etchable block removed by etching. Then a laser cuts through the semiconductor border region forming an empty space by removal of the continuous etchable block to separate the first chip from the second chip.
The Abstract of Japanese Patent Publication 2005-109322 of Yakasuki et al describes a “Laser Beam Dicing Device” with the laser head of a laser beam dicing device that includes a plurality of laser oscillators and light-condensing means which condense oscillated laser light beams individually and an optical path collecting means which collects the laser light beams onto one optical axis. The laser beam dicing device is useful with various processes, e.g. formation of a multilayered reformed area in a wafer, a composite process by which the formation of the reformed area in the wafer and the cutting of the die attaching tape are performed simultaneously, or the like, with the laser light beams converging at different positions.
In Guthrie, an air gap is described formed in a structure that extends to the active device region to the edge of a gate electrode and over the edge thereabove but not reaching down to the surface of the substrate therebelow. We have discovered that there is a problem that such a structure cannot prevent delaminations.
Fitzsimmons et al provides a void down to a cap layer with no indication of what is formed below the cap layer. The application initially mentions substrates but fails to show a substrate or indicate what is below the cap layer.
As stated above, a key requirement for preventing these new failure mechanisms described above is to limit the propagation distance that a flaw (generated during the dicing process) can propagate before it encounters the barrier (crackstop/MOB) structure. While there are a number of potential solutions to this problem, heretofore all solutions known require either a loss in productivity (reduction in number of chips per wafer) or a loss in I/O density (due to a redesign of a Controlled Collapse Chip Connection (C4) layout).